1. Technical Field
This invention is directed to a process for fabricating integrated circuit devices and, in particular, to semiconductor devices that have copper interconnects.
2. Art Background
As devices are scaled to sub-micron dimensions, formation of reliable sub-micron interconnection (interconnects) becomes increasingly difficult. Many techniques have been used to form interconnects. However, as the dimensions of sub-micron interconnects get smaller, current techniques are becoming less useful.
For example, techniques that require the interconnects to be formed by patterning a layer of metal using lithographic techniques, in which the pattern defined in a layer of energy sensitive material is transferred into the underlying metal layer by etch expedient, have several problems. In these techniques, contact holes (windows or vias) are formed in a layer of a dielectric material. The contact holes are then filled with metal by depositing a metal layer over the dielectric layer. The portion of the deposited metal layer overlying the dielectric layer is then removed using an expedient such as etching or chemical mechanical polishing (CMP). The portion of the metal layer that remains is the portion in the contact holes formed in the dielectric layer.
A second layer of metal is then formed over the dielectric layer with the metal-filled contact holes. The second metal layer is patterned to form the interconnect wires in the conventional subtractive process. Typically the metal filling the contact holes is one metal (e.g., CVD (chemical vapor deposited) tungsten) and the patterned metal is a second metal (e.g., aluminum). The second metal layer is patterned using lithographic techniques.
Such a process has certain problems associated therewith. Specifically, the patterned aluminum layer is subject to sidewall corrosion. Also, the spaces between the patterned metal lines must be subsequently filled with a dielectric layer before further processing. Furthermore, the use of dissimilar metals for the interconnects (e.g., tungsten) and the wires (e.g., aluminum) adversely affects both the mechanical strength and the electrical quality of the interconnect.
Copper is currently under investigation as an interconnect material because it has a low cost and a low resistivity. However, it is difficult to etch copper. Therefore processes that require the metal interconnect to be etched are not useful for forming copper interconnects. A promising technique for forming interconnects is a dual damascene process (or a combination of two single damascene processes). In a dual damascene process a single dielectric layer is deposited and patterned using a two-step etch process. The first step etches contact openings through half or more of the dielectric layer thickness and the second etch step etches the contact openings through the remaining dielectric thickness to the underlying layer and also the interconnect channels (i.e., trenches) part way through the dielectric layer.
The dual damascene process is advantageous for copper interconnect formation compared to the conventional subtractive process because in dual damascene, lithographic techniques and etching expedients are not required to pattern a layer of copper. However, in dual damascene, copper deposition is complicated because the contact openings may have an aspect ratio (i.e. the ratio of the height to the width of the recess) of 2:1, 3:1, or more. The high aspect ratio makes sputter deposition difficult. Copper may be deposited by CVD within the contact openings and interconnect channels. However, copper is difficult and/or expensive to deposit by CVD. As a result, copper is not typically deposited by CVD in production.
Electroless metal deposition (i.e., electroless plating) has been investigated as a technique for depositing copper onto a patterned layer of dielectric material. In this technique the surfaces to be plated (e.g., contact openings (windows or vias) and interconnect channels) must be pretreated before the metal is deposited in order to effect electroless deposition. Low deposition rates and issues of bath stability make this approach unattractive for use in production. In addition, current surface activation techniques such as physical vapor deposition (PVD, e.g., sputtering) of a catalytic metal or treatment with an activating solution are either difficult or incompatible with current processes for device fabrication.
A major advantage of copper is its relatively low cost and low resistivity. However, it has a relatively large diffusion coefficient into silicon, silicon dioxide, and low dielectric constant polymers such as polyimide. Copper from an interconnect may diffuse through the silicon dioxide or polymer layer and into the underlying silicon. Copper diffusion into the underlying silicon substrate can degrade the transistor characteristics of the resulting device. Copper interconnects should be encapsulated by at least Ione diffusion barrier to prevent diffusion into the silicon dioxide layer. The formation of this diffusion barrier is another problem associated with copper interconnect formation.
As noted in U.S. Pat. No. 5,627,102 to Shinriki et al., one problem associated with the formation of metal interconnects is that voids form in the metal filling the recess. Such faulty fill-up leads to a failure to establish a sound electrical contact. The problem of faulty fill-up increases with increasing aspect ratios. Consequently, as the width of the recess decreases, the problems associated with faulty fill-up increase.
Accordingly, a process for making copper interconnects that addresses the current problems associated with copper interconnect formation is desired.